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| CDP1821C/3 March 1997 High-Reliability CMOS 1024-Word x 1-Bit Static RAM Description The CDP1821C/3 is a 1024-word x 1-bit CMOS silicon-on-sapphire (SOS), fully static, random-access memory designed for use in CDP1800 microprocessor systems. This device has a recommended operating voltage range of 4V to 6.5V. The output state of the CDP1821C/3 is a function of the input address and chip-select states only. Valid data will appear at the output in one access time following the latest address change to a selected chip. After valid data appears, the address may be changed immediately. It is not necessary to clock the chip-select input or any other input terminal for fully static operation; therefore the chip-select input may be used as an additional address input. When the device is in an unselected state (CS = 1), the internal write circuitry and output sense amplifier are disabled. This feature allows the three-state data outputs from many arrays to be OR-tied to a common bus for easy memory expansion. Features * Static CMOS Silicon-On-Sapphire Circuitry CD4000Series Compatible * Compatible with CDP1800-Series Microprocessors at Maximum Speed * Fast Access Time. . . . . . . . . . . 100ns Typ. at VDD = 5V * Single Voltage Supply * No Precharge or External Clocks Required * Low Quiescent and Operating Power * Separate Data Inputs and Outputs * High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD * Memory Retention for Standby Battery Voltage Down to 2V at +25oC * Latch-Up-Free Transient-Radiation Tolerance Ordering Information PACKAGE SBDIP TEMP. RANGE -55oC to +125oC PART NUMBER CDP1821CD3 PKG. NO. D16.3 Pinout CDP1821C/3 (SBDIP) TOP VIEW CS A0 A1 A2 A3 A4 DO VSS 1 2 3 4 5 6 7 8 16 VDD 15 DI 14 RD/WR 13 A9 12 A8 11 A7 10 A6 9 A5 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 File Number 2983.1 6-5 CDP1821C/3 Functional Block Diagram CS R/W ROW BUFFERS A0 a0 1/16 ROW DECODER a3 CS * R/W * A4 COL. 0 16 x 32 CELL ARRAY COL. 31 ROW 0 VDD ROW 15 A3 DI A5 A9 DI a0 COLUMN BUFFERS A4 1/32 COLUMN DECODER A4 DO CS * R/W * A4 1/16 ROW DECODER COLUMN BUFFERS ROW 16 16 x 32 CELL ARRAY ROW 31 COL. 0 COL. 31 VSS a3 ROW BUFFERS OPERATIONAL MODES INPUTS MODE Standby Write Read X = Don't Care READ/WRITE R/W X 0 1 Logic 1 = High Logic 0 = Low CHIP-SELECT CS 1 0 0 OUTPUT DATA OUTPUT DO High Impedance High Impedance Contents of Addressed Call 6-6 CDP1821C/3 Absolute Maximum Ratings DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA Thermal Information Thermal Resistance (Typical) JA (oC/W) JC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 75 20 Maximum Operating Temperature Range (TA) . . . .-55oC to +125oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Lead Temperature (During Soldering) . . . . . . . . . +265oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150oC Recommended Operating Conditions TA = Full Package-Temperature Range. For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges: CDP1821CD/3 PARAMETER DC Operating Voltage Range Input Voltage Range VDD = 5V 5% MIN 4 VSS MAX 6.5 VDD UNITS V V Static Electrical Specifications -55oC, +25oC PARAMETER Quiescent Device Current (Note 1) Output Low Drive (Sink) Current (Note 1) Output High Drive (Source) Current (Note 1) Output Voltage Low-Level Output Voltage High-Level Input Low Voltage Input High Voltage Input Current (Note 1) Three-State Output Leakage Current (Note 1) Operating Current (Note 2) Input Capacitance Output Capacitance NOTES: SYMBOL IDD IOL IOH CONDITIONS VIN = 0V or VDD VOUT = 0.4V VOUT = VDD -0.4V MIN 2.7 -1.3 MAX 260 - +125oC MIN 1.6 -0.8 MAX 1000 UNITS A mA mA VOL VOH VIL VIH IIN IOUT VIN = 0V or VDD VIN = 0V or VDD VDD -0.1 0.7 VDD - 0.1 0.3 VDD 2.6 2.6 VDD -0.5 0.7 VDD - 0.5 0.3 VDD 10 10 V V V V A A IDD1 CIN COUT - - 5 7.5 15 - 10 7.5 15 mA pF pF 1. Limits designate 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing 2. Measured with 1s read-cycle time and outputs floating. 6-7 CDP1821C/3 Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF -55oC, +25oC PARAMETER Data Access Time (Note 1) Read Cycle Time Output Enable Time Output Disable Time NOTE: 1. 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing. SYMBOL tDA tRC tEN tDIS VDD (V) 5 5 5 5 MIN 190 65 MAX 190 65 MIN 255 90 +125oC MAX 255 90 UNITS ns ns ns ns CS (NOTE 1) tDOA (NOTE 2) A0 - A9 tRC R/W (NOTE 3) (NOTE 4) tDOH (NOTE 5) DATA OUT VALID HIGH IMPEDANCE DATA OUT (NOTE 5) tAA NOTES: 1. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device. 2. Chip-Select (CS) permitted to change from low to high level or remain low. 3. Read/Write (R/W) must be at a high level during all address transitions. 4. Don't care. 5. Data-Out (DO) is a high impedance within tDIS ns after the falling edge of R/W or the rising edge of CS. FIGURE 1. READ CYCLE TIMING DIAGRAM 6-8 CDP1821C/3 Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF -55oC, +25oC PARAMETER Write Cycle Time Address Setup Time (Note 1) Address Hold Time (Note1) Input Data Setup Time (Note 1) Input Data Hold Time (Note 1) Read/Write Pulse Width Low (Note 1) NOTE: 1. 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing. SYMBOL tWC tAS tAH tDS tDH tWL VDD (V) 5 5 5 5 5 5 MIN 300 60 130 90 60 110 MAX MIN 420 84 180 125 84 155 +125oC MAX UNITS ns ns ns ns ns ns CS (NOTE 1) (NOTE 2) A0 - A9 tWC tWL R/W (NOTE 3) tAS tDS tDH tAH DI (NOTE 3) (NOTE 3) NOTES: 1. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device. 2. Chip-Select (CS) permitted to change from low to high level or remain low. 3. Don't care. FIGURE 2. WRITE CYCLE TIMING DIAGRAM 6-9 CDP1821C/3 Data Retention Specifications TEST CONDITIONS VDR (V) VDD (V) -55oC, +25oC +125oC PARAMETER Minimum Data Retention Voltage (Note 1) Data Retention Quiescent Current (Note 1) Chip Deselect to Data Retention Time Recovery to Normal Operation Time NOTE: SYMBOL VDD MIN - MAX 2 MIN - MAX 2.5 UNITS V IDD 2 - - 50 - 200 A tCDR tRC - 5 5 450 450 - 650 650 - ns ns 1. 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing DATA RETENTION MODE VDD 0.95 VDD VDR tCDR tF tR tRC 0.95 VDD CS VIH VIL VIH VIL FIGURE 3. LOW VDD DATA RETENTION WAVEFORMS AND TIMING DIAGRAM Burn-In Circuit R A11 A0 A1 A2 A3 A4 VDD/2 RI R R R R R 1 2 3 4 5 6 7 8 16 15 14 13 12 11 R 10 R 9 A5 VDD R = 8.2k 20% RI = 2k 20% A1 0 A6 R R R R R VDD A10 O1 A9 A8 A7 A0 0 VDD O1 0 VDD 0 1.6 2.2 5.0 6.6 7.2 10.0 s PACKAGE D VDD 7V TEMPERATURE +125oC DURATION 160 Hrs. A1 - A11 ARE DIVISION BY 2 BASED ON A0 FIGURE 4. DYNAMIC/OPERATING BURN-IN CIRCUIT AND TIMING DIAGRAM 6-10 CDP1821C/3 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 6-11 |
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